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MDT10P22(DF)
1. General Description This EPROM-Based 8-bit micro-controller uses a fully static CMOS design technology to achieve high speed, small size, low power and high noise immunity. On chip memory includes 1K words EPROM and80 bytes static RAM. Four comparator inputs with external Vref (not for 18 pin package) are also provided. 2. Features Fully CMOS static design 8-bit data bus On chip EPROM size : 1 K words Internal RAM size : 80 bytes (72 general purpose registers, 8 special registers) 36 single word instructions 14-bit instructions 2-level stacks Operating voltage : 2.3V ~ 6.0 V Operating frequency : 0 ~ 20 MHz The most fast execution time is 200 ns under 20 MHz in all single cycle instructions except the branch instruction Addressing modes include direct, indirect and relative addressing modes Power-on Reset (POR), only available while PED is Disable 4 Channel comparator Power edge-detector Reset Sleep Mode for power saving 8-bit real time clock/counter(RTCC) with 8-bit programmable prescaler 4 types of oscillator can be selected by
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programming option: RCLow cost RC oscillator LFXTLow frequency crystal oscillator XTALStandard crystal oscillator HFXTHigh frequency crystal oscillator 4 oscillator start-up time can be selected by programming option: 150 s, 20 ms, 40 ms, 80 ms On-chip RC oscillator based Watchdog Timer(WDT) can be operated freely 12 I/O(for 18 pins package),14 I/O(for 20 pins package),16 I/O(for 22/24 pins package) pins with their own independent direction control 3. Applications The application areas of this MDT10P22 range from appliance motor control and high speed automotive to low power remote transmitters/receivers, pointing devices, and telecommunications processors, such as Remote controller, small instruments, chargers, toy, automobile and PC peripheral ... etc
This specification are subject to be changed without notice. Any latest information
P. 1
2007/8
Ver. 1.6
MDT10P22(DF)
4. Pin Assignment A120PINS, A222PINS, A324PINS, A5 :18 PINS PPDIP,SSOP, KSKINNY A1P,A1S PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 PB1 PB2 PB3 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 11 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4 NC 1 PA7 2 PA5 3 PA2/CIC2 4 PA3/CIC3 5 RTCC 6 /MCLR 7 Vss 8 PB0 9 PB1 10 PB2 11 PB3 12 A3S 24 23 22 21 20 19 18 17 16 15 14 13 NC PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6 PB5 PB4
A2K A5P,A5S PA7 PA5 PA2/CIC2 PA3/CIC3 RTCC /MCLR Vss PB0 1 2 3 4 5 6 7 8 22 21 20 19 18 17 16 15 PA6 PA4/VREF PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PA2CIC2 1 PA3/CIC3 2 RTCC 3 /MCLR 4 Vss 5 PB0 6 PB1 7 PB2 8 PB3 9 18 17 16 15 14 13 12 PA1/CIC1 PA0/CIC0 OSC1 OSC2 Vdd PB7 PB6
PB1 9 PB2 10 PB3 11
14 PB6 13 PB5 12 PB4
11 PB5 10 PB4
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P. 2
2007/8
Ver. 1.6
MDT10P22(DF)
5. Block Diagram
S ta ck Two Le ve ls
EP RO M 1Kx14 (MDT10P 22)
RAM 72x8 P ort B
P ort P B0~P B7 8 bits
10 bits 10 bits P rogra m Counte rs Ins truction Re gis te r 14 bits
S pe cia l Re gis te r
O S C2 OS C1 MCLR
D0~D7 P ort A Ins truction De code r
P ort P A0~P A7 (22,24 pins ) P A0~P A5 (20 pins ) P A0~P A3 (18 pins ) 8 bits
Os cilla tor Circuit
Control Circuit CMR0~C MR5 Com pa ra t or m ode Re gis te r
P owe r on Re s e t P owe r Down Re s e t Working Re gis te r ALU
Da ta 8-bit
S ta tus Re gis te r
8-bit Tim e r/Counte r
P re s ca le
WDT/OS T Tim e r
RTCC
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P. 3
2007/8
Ver. 1.6
MDT10P22(DF)
6. Pin Function Description Pin Name PA0~PA7 I/O I/O Function Description PA0~PA3 : TTL input level or comparator input PA4 : TTL input level or comparator VREF input PA5~PA7 : TTL input level Port B, TTL input level Real Time Clock/Counter, Schmitt Trigger input levels Master Clear, Schmitt Trigger input levels Oscillator Input Oscillator Output Power supply Ground Unused ,do not connect
PB0~PB7 RTCC /MCLR OSC1 OSC2 Vdd Vss NC
I/O I I I O
7. Memory Map (A) Register Map Address 00 01 02 03 04 05 06 07 08~0F 10~1F 30~3F 50~5F 70~7F Description Indirect Addressing Register RTCC PC STATUS MSR Port A Port B Control register for comparator Internal RAM, General Purpose Register Internal RAM, Memory bank 0 Internal RAM, Memory bank 1 Internal RAM, Memory bank 2 Internal RAM, memory bank 3
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P. 4
2007/8
Ver. 1.6
MDT10P22(DF)
(1) IAR ( Indirect Address Register) : R0 (2) RTCC (Real Time Counter/Counter Register) : R1 (3) PC (Program Counter) : R2 Write PC, CALL --- always 0 LJUMP, JUMP, LCALL --- from instruction word RTWI, RET --- from STACK
A9
A8
A7~A0
Write PC, JUMP, CALL --- from STATUS b5 LJUMP, LCALL --- from instruction word RTWI, RET --- from STACK Write PC --- from ALU LJUMP, JUMP, LCALL, CALL --- from instruction word RTWI, RET --- from STACK (4) STATUS (Status register) : R3 Bit 0 1 2 3 4 5 Symbol C HC Z PF TF page Carry bit Half Carry bit Zero bit Power loss Flag bit Time overflow Flag bit ROM Page select bit : 00 : 000H --- 1FFH 01 : 200H --- 3FFH 7 ---- General purpose bit Function
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P. 5
2007/8
Ver. 1.6
MDT10P22(DF)
(5) MSR (Memory Select Register) : R4 Memory Select Register : 00 : 10~1F 01 : 30~3F 10 : 50~5F 11 : 70~7F
b7
b6
b5
b4
b3
b2
b1
b0
Read only "1" Indirect Addressing Mode (6) PORT A : R5 PA7~PA0, I/O Register for 22, 24 pins PA5~PA0, I/O Register for 20 pins PA3~PA0, I/O Register for 18 pins (7) PORT B : R6 PB7~PB0, I/O Register (8) CMR(Comparator Mode Register) : R7 Bit 0 1 2 3 5:4 Function 0: Define PA0 as TTL input 1: Define PA0 as comparator input 0: Define PA1 as TTL input 1: Define PA1 as comparator input 0: Define PA2 as TTL input 1: Define PA2 as comparator input 0: Define PA3 as TTL input 1: Define PA3 as comparator input Reference Voltage select 00: 1/4 VDD 01: 1/2 VDD 10: 3/4 VDD 11: VREF (External pin and PA4 must be set to inpu 7:6 Register bits
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P. 6
2007/8
Ver. 1.6
MDT10P22(DF)
(9) TMR (Time Mode Register) Bit Symbol Prescaler Value Function RTCC rate WDT rate 000 1:2 1:1 001 1:4 1:2 010 1:8 1:4 011 1 : 16 1:8 100 1 : 32 1 : 16 101 1 : 64 1 : 32 110 1 : 128 1 : 64 111 1 : 256 1 : 128 Prescaler assignment bit : 0 -- RTCC 1 -- Watchdog Timer RTCC signal Edge : 0 -- Increment on low-to-high transition on RTCC pin 1 -- Increment on high-to-low transition on RTCC pin RTCC signal set : 0 -- Internal instruction cycle clock 1 -- Transition on RTCC pin
2--0
PS2--0
3
PSC
4
TCE
5
TCS
(10) CPIO A, CPIO B (Control Port I/O Mode Register) The CPIO register is "write-only" "0", I/O pin in output mode; "1", I/O pin in input mode. (11) EPROM Option by writer programming : A. FIRST WORD Oscillator Type RC Oscillator Oscillator Start-up Time 150 s 20 ms 40 ms 80 ms
LFXT Oscillator XTAL Oscillator HFXT Oscillator Watchdog Timer control Watchdog timer disable all the time Watchdog timer enable all the time
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P. 7
2007/8
Ver. 1.6
MDT10P22(DF)
Power Edge Detect PED Disable PED Enable (B) Program Memory Address 000- 3FF 3FF Program memory The starting address of the power on, external reset or WDT Description Security bit Security Disable Security Enable
8. Reset Condition for all Registers Register CPIO A CPIO B TMR IAR RTCC PC STATUS MSR PORT A PORT B CMR Address 00h 01h 02h 03h 04h 05h 06h 07h Power-On Reset /MCLR Reset 1111 1111 1111 1111 --11 1111 xxxx xxxx 1111 1111 0001 1xxx 100x xxxx xxxx xxxx xxxx xxxx 0000 0000 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 100u uuuu uuuuuuuu uuuu uuuu uuuu uuuu WDT Reset 1111 1111 1111 1111 --11 1111 uuuu uuuu 1111 1111 000# #uuu 1uuu uuuu uuuu uuuu uuuu uuuu uuuu uuuu
Note : uunchanged, xunknown, - unimplemented, read as "0" #value depends on the condition of the following table Condition /MCLR reset (not during SLEEP) /MCLR reset during SLEEP WDT reset (not during SLEEP) WDT reset during SLEEP Status: bit 4 U 1 0 0 Status: bit 3 u 0 1 0
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P. 8
2007/8
Ver. 1.6
MDT10P22(DF)
9. Instruction Set Mnemonic Operands NOP CLRWT SLEEP TMODE RET CPIO STWR LDR LDWI I SWAPR R, t INCR R, t R R R, t
Instruction Code 010000 00000000 010000 00000001 010000 00000010 010000 00000011 010000 00000100 010000 00000rrr 010001 1rrrrrrr 011000 trrrrrrr 111010 iiiiiiii 010111 trrrrrrr 011001 trrrrrrr 011010 trrrrrrr 011011 trrrrrrr 011100 trrrrrrr 011101 trrrrrrr 011110 trrrrrrr 010010 trrrrrrr 110100 iiiiiiii 010011 trrrrrrr 110101 iiiiiiii 010100 trrrrrrr 110110 iiiiiiii 011111 trrrrrrr 010110 trrrrrrr 010101 trrrrrrr 010000 1xxxxxxx 010001 0rrrrrrr 0000bb brrrrrrr
Function No operation Clear Watchdog timer Sleep mode Return Control I/O port register Store W to register Load register Load immediate to W Swap halves register Increment register Increment register, skip if zero Add W and register Subtract W from register Decrement register
Operating None 0WT
Status
TF, PF None None r None None Z None None Z None C, HC, Z C, HC, Z Z None Z Z Z Z Z Z Z C C Z Z None
0WT, stop OSC TF, PF StackPC WCPIO WR Rt IW [R(0~3)R(4~7)] t R + 1t R + 1t W + Rt R Wt (R+/W+1t) R 1t R 1t R Wt i WW R Wt R Wt i WW /Rt R(n) R(n-1), C R(7), R(0)C R(n)r(n+1), CR(0), R(7)C 0W 0R 0R(b)
Load W to TMODE register WTMODE
INCRSZ R, t ADDWR R, t SUBWR R, t DECR R, t
DECRSZ R, t Decrement register, skip if zero ANDWR R, t AND W and register ANDWI i IORWR R, t IORWI i XORWR R, t XORWI i COMR RRR RLR CLRW CLRR BCR R R, b R, t R, t R, t AND W and immediate Inclu. OR W and register Exclu. OR W and register Exclu. OR W and immediate Complement register Rotate right register Rotate left register Clear working register Clear register Bit clear
Inclu. OR W and immediate i WW
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P. 9
2007/8
Ver. 1.6
MDT10P22(DF)
Instruction Code 0010bb brrrrrrr 0001bb brrrrrrr 0011bb brrrrrrr Mnemonic Operands BSR BTSC BTSS R, b R, b R, b Bit set Bit Test, skip if clear Bit Test, skip if set Long CALL subroutine Long JUMP to address Call subroutine Return, place immediate to W JUMP to address Function Operating 1R(b) Skip if R(b)=0 Skip if R(b)=1 nPC, PC+1 Stack nPC nPC, PC+1 Stack StackPC,iW nPC Status None None None None None None None None
100nnn nnnnnnnn LCALL n 101nnn nnnnnnnn LJUMP n 110000 nnnnnnnn CALL 110001 iiiiiiii RTWI n i n
11001n nnnnnnnn JUMP Note : W WT TMODE CPIO TF PF PC OSC Inclu. Exclu. AND : : : : : : : : : : :
Working register Watchdog timer TMODE mode register Control I/O port register Timer overflow flag Power loss flag Program Counter Oscillator Inclusive `' Exclusive `' Logic AND `'
b t
: : 0 1 R: C: HC : Z: / : x : i : n:
Bit position Target : Working register : General register General register address Carry flag Half carry Zero flag Complement Don't care Immediate data ( 8 bits ) Immediate address
10. Electrical Characteristics (Operating temperature at 25). Sym Description Condition Min 2.3 Vdd=5V Vdd=5V Vdd=5V Vdd=5V Vdd=5V Vdd=5V, IOL=20mA Vdd=5V, IOL=5mA 0.5 0.1 -0.6 -0.6 2.0 3.3 Typ Max 6.0 1.0 1.0 Vdd Vdd +/-1 Unit V V V V V A V V Vdd Operating voltage VIL Input Low Voltage PA, PB RTCC, /MCLR VIH Input high Voltage PA, PB RTCC, /MCLR IIL Input leakage current VOL Output Low Voltage PA, PB
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P. 10
2007/8
Ver. 1.6
MDT10P22(DF)
Sym Description Condition Vdd=5V, IOH= -20mA Vdd=5V, IOH= -5mA Vdd2.3 ~ 6.0 V Vdd2.3 V Vdd3.0 V Vdd4.0 V Vdd5.0 V Vdd6.0 V 1.1 25.2 22.4 20.4 18.8 18.0 600 15 Vdd-0.8 v 8 8 8 8 Min Typ 3.8 4.5 0.1 1 3 6 11 17 1.3 1.0 Max Unit V V A A A A A A V mS mS mS mS mS nS A V
VOH Output High Voltage PA, PB
Islp Sleep current (WDT disable) Islp Sleep current (WDT enable)
Vpr Power Edge-detector Reset Voltage Twdt The basic WDT time-out cycle Vdd2.3 V Vdd3.0 V time Vdd4.0 V Vdd5.0 V Vdd6.0 V TFLT /MCLR filter Icc Comparator Supply current (one comparator) Vref Input reference voltage Comparator Response time V-=Vdd/4, V+=V- 0.2v V-=Vdd/2, V+=V- 0.2v V-=Vdd3/4, V+=V- 0.2v V-=VDD-0.8,V+=V 0.2v Vdd5.0 V Vdd=5.0v Vdd=2.5v ~6.0v Vdd=5.0v , V- = Vref V+ = (PA0~PA3)
---
S S S S
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P. 11
2007/8
Ver. 1.6
MDT10P22(DF)
11. Operating Current Temperature25 , the typical value as followings : 11.1 OSC TypeRC ; WDTEnable; @ Vdd5.0 V ; PED=Disable Cext. (F) Rext. (Ohm) 4.7 K 10.0 K 3P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 20P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 100P 47.0 K 100.0 K 300.0 K 470.0 K 4.7 K 10.0 K 300P 47.0 K 100.0 K 300.0 K 470.0 K Frequency (Hz) 11.2 M 5.95 M 1.40M 658 K 225 K 141 K 5.45 M 2.75 M 625 K 295 K 100 K 64 K 1.77 M 885 K 195 K 92 K 31 K 20 K 685 K 337 K 75 K 35 K 12 K 7K Current (A) 1.2 mA 655 A 235 A 165 A 140 A 120 A 620 A 370 A 172 A 140 A 125 A 120 A 290 A 210 A 145 A 135 A 130 A 125 A 190 A 158 A 135 A 130 A 126 A 125 A
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P. 12
2007/8
Ver. 1.6
MDT10P22(DF)
11.2 OSC TypeLF (OSC1&OSC2 External Cap about 10P); WDTDisable ; PED=Disable Voltage/Frequency 2.3 V 3.0 V 4.0 V 5.0 V 6.0 V 32 K (EXT100P) 7.0A 15.0A 35.0A 73.0A 132.0A 455 K (EXT50P) 2.6V@25.0 A 55A 90A 145A 220A 1M 40A 70A 120A 185A 265A Sleep 1.0 A 1.0 A 1.0 A 1.0 A 1.0 A
11.3 OSC TypeXT (OSC1&OSC2 EXternal Cap about 10P); WDTEnable PED=Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V 1M 50A 105A 215A 380A 650A 4M 120A 235A 405A 600A 855A 10 M 290A 500A 650A 1.3mA 1.7mA Sleep 1.0 A 3 A 6 A 11 A 17 A
11.4 OSC TypeHF (OSC1&OSC2 External Cap about 10P); WDTEnable PED=Disable Voltage/Frequency 2.1 V 3.0 V 4.0 V 5.0 V 6.0 V 4M 150A 290A 510A 800A 1.4mA 10 M 320A 550A 910A 1.5mA 2.0mA 20 M X 930A 1.5mA 2.4mA 3.3mA Sleep 1.0 A 3 A 6 A 11 A 17 A
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P. 13
2007/8
Ver. 1.6
MDT10P22(DF)
11.5 Power Edge-detector Reset Voltage (Not in Sleep Mode), @ Vdd5.0 V (PED : Enable ) Vpr1.6~1.8 V Vpr Vdd (Power Supply)
PS. If PED_Enable then Internal Power_on_reset will be off 12. Port A Equivalent Circuit
PA0-PA3
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G QB
Port I/O Pin
Write
Input Resistor
Data Bus QB Rea d D Data I/P Latch G S
0 TTL input level
+ 1 comparator level VREF
Compartor Control
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P. 14
2007/8
Ver. 1.6
MDT10P22(DF)
PA4
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G Q B Input Resistor Data Bus Rea d QB Data I/P Latch G D TTL Input Level
Port I/O Pin
Write
comparator enable
3 2 Vref S0 S1 CMR_4 CMR_5 1 0
3/4 VDD 1/2 VDD 1/4 VDD
PA5-PA7
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G Q B
Port I/O Pin
Write
Data Bus Rea d
QB Data I/P Latch G
D Input Resistor TTL Input Level
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P. 15
2007/8
Ver. 1.6
MDT10P22(DF)
Port B Equivalent Circuit
D I/O Control Latch
Q
I/O Control
C K
Q B
D Data O/P Latch G Q B
Port I/O Pin
Write
Data Bus Rea d
QB Data I/P Latch G
D Input Resistor TTL Input Level
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P. 16
2007/8
Ver. 1.6
MDT10P22(DF)
13. MCLRB and RTCC Input Equivalent Circuit
R1K
MCLRB Schmitt Trigger
R1K
RTCC Schmitt Trigger
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P. 17
2007/8
Ver. 1.6
MDT10P22(DF)
14. External Capacitor Selection For Crystal Oscillator @ Vdd5.0 V Osc. Type Resonator Freq. 20 MHz HF 10 MHz 4 MHz 10 MHz XT 4 MHz 1 MHz 1 MHz LF 455 K 32 K Capacity Range 10 pF ~ 50 pF 20 pF ~ 50 pF 10 pF ~ 30 pF 10 pF ~ 50 pF 10 pF ~ 50 pF 20 pF ~50 pF 20 pF ~ 30 pF 20 pF ~30 pF 20 pF ~30 pF
MDT10P22
OSC1 OSC2
C1
C2
To increase the stability of oscillator and the ability of anti-noise, the above values of the external capacitor are for reference only, but the higher capacitance also increases the start-up time.
This specification are subject to be changed without notice. Any latest information please preview http;//www.mdtic.com.tw
P. 18
2007/8
Ver. 1.6

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